OcrV1, Main, Exploration, bibRecord, 000157

Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters

Identifieur interne : 000157 ( Main/Exploration ); précédent : 000156; suivant : 000158

Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters

Auteurs : Cesar Torres-Huitzil [Mexique]

Source :

The Scientific World Journal [ 1537-744X ] ; 2013.

RBID : PMC:3833061

Abstract

Running max/min filters on rectangular kernels are widely used in many digital signal and image processing applications. Filtering with a k × k kernel requires of k² − 1 comparisons per sample for a direct implementation; thus, performance scales expensively with the kernel size k. Faster computations can be achieved by kernel decomposition and using constant time one-dimensional algorithms on custom hardware. This paper presents a hardware architecture for real-time computation of running max/min filters based on the van Herk/Gil-Werman (HGW) algorithm. The proposed architecture design uses less computation and memory resources than previously reported architectures when targeted to Field Programmable Gate Array (FPGA) devices. Implementation results show that the architecture is able to compute max/min filters, on 1024 × 1024 images with up to 255 × 255 kernels, in around 8.4 milliseconds, 120 frames per second, at a clock frequency of 250 MHz. The implementation is highly scalable for the kernel size with good performance/area tradeoff suitable for embedded applications. The applicability of the architecture is shown for local adaptive image thresholding.

Url:

http://www.ncbi.nlm.nih.gov/pmc/articles/PMC3833061

DOI: 10.1155/2013/108103
PubMed: 24288456
PubMed Central: 3833061

Affiliations:

Mexique

Le document en format XML

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Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters

Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters

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Abstract

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